Senior DFT Engineer
November 16
Description
• Join one of Europe’s premier semiconductor startups as a pivotal member of the DFT team. • Contribute to the success of Axelera's multicore in-memory-compute SoC. • Architect, design, and implement cutting-edge testability infrastructure. • Drive advancements in testability methodologies and infrastructure.
Requirements
• Senior-level expertise in Design for Test (DFT) engineering. • Skilled in SystemVerilog RTL, TCL, Python. • Comfortable working in Unix/Linux environments. • Hierarchical scan and scan compression. • Memory BIST. • JTAG/IJTAG. • At-speed test. • ATPG (Automatic Test Pattern Generation). • Fault simulation. • Back-annotated gate-level verification. • Silicon debug. • Familiarity with Siemens, Cadence, and/or Synopsys DFT tools. • Exceptional technical problem-solving and debugging skills. • Fluent in English, both spoken and written.
Benefits
• Attractive compensation package, including pension plan. • Extensive employee insurances. • Option to get company shares. • Open culture supporting creativity and innovation. • Collaborative ownership and freedom with responsibility.
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