Senior ASIC Ethernet Design Engineer

December 31, 2024

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Cornelis Networks

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Cornelis Networks is a leading provider of intelligent, scalable, high-performance interconnects designed for AI applications. The company specializes in delivering end-to-end purpose-built high-performance fabrics to commercial, scientific, academic, and government organizations. Cornelis Networks’ solutions are aimed at enhancing performance, scalability, and efficiency across hyperscale, cloud AI, and on-premises AI/HPC environments. Their offerings are known for scalable architecture, high bandwidth solutions, and universal compatibility with accelerators and GPUs. Originating as an Intel spin-off, the company is positioned to challenge existing technologies like InfiniBand and Ethernet, providing advanced interconnects that power modern AI infrastructure.

51 - 200 employees

🤖 Artificial Intelligence

🔧 Hardware

🏢 Enterprise

💰 $29M Series B on 2022-11

📋 Description

• Cornelis Networks is hiring talented Sr. ASIC Design Engineers with deep experience in one or more of the key areas required to build the world-class SoCs to be deployed in high performance computing, high performance data analytics, and artificial intelligence interconnect solutions. • A good candidate will have 15+ years of ASIC design experience, with 10+ years of relevant experience in networking hardware design, proven expertise in 50G, 100G, 400G Ethernet MAC/PCS protocols, TCP/IP, RDMA/RoCE, IPSec. • Key Responsibilities include end-to-end SoC/ASIC development, front-end standard cell ASIC development including RTL development, Design Verification, synthesis, and post-silicon validation. • Cross-functional collaboration and partnering with internal and external cross-functional teams, across all levels of the corporation. • Define, implement, debug, and deliver system solutions around purpose-built ASICs.

🎯 Requirements

• 15+ years' post-college experience with silicon development. • 15+ years' post-college experience in digital design with one or more HDL language (System Verilog, Verilog, VHDL). • 10+ years of relevant experience in networking hardware design, proven expertise in 50G, 100G, 400G Ethernet MAC/PCS protocols, TCP/IP, RDMA/RoCE, IPSec. • 5 + years' post-college experience in one or more scripting language (TCL, Python, Perl). • Understanding of Standard Cell ASIC development flow including digital design, IP integration, simulation and synthesis. • B.S. degree in Computer Engineering, Computer Science, or Electrical Engineering.