HW Verification Engineer
November 12
Description
• verify industrial-grade open-source IPs based on RISC-V • work closely with the Eclipse Research Team and OpenHW Technical Working Group • contribute to the TRISTAN project • address SW to EDA tools and RTL components
Requirements
• confident with SystemVerilog and UVM • knowledge of Linux, Make, and Python • understanding of computer architectures of general-purpose CPUs • familiarity with peripheral busses, interrupt controllers, and peripherals such as UART, SPI, and GPIOs • experience with a commercial SystemVerilog simulator and associated debug and coverage tools • familiarity with Formal Verification, RTL design, RISC-V ISA, and Git
Benefits
• Friday flex-time • right-to-disconnect policy • Corporate Recharge days • highly competitive compensation • comprehensive benefits package
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