Staff Digital Design Verification Engineer
August 29
Description
• Work on verification of a proprietary cryptographic processor and SoC • Contribute to the architecture and methodology of our DV environment and team from scratch • Develop and execute verification plans and testbenches to validate the functionality of our products • Write and maintain directed and constrained random tests to ensure that the verification environment is up-to-date and effective • Work cross functionally to integrate the verification environment into the overall design flow. • Own and develop formal and UVM verification methods to ensure the completeness and consistency of the design. • Provide technical guidance to other team members with the latest verification best practices and techniques.
Requirements
• BS, MS, & PhD in Electrical Engineering, Computer Science, or a related field. • 10+ years of strong experience with design verification • Integration of third-party IP into an SoC • Experience with an SoC through tapeout and post-silicon • Knowledge of CDC, XProp, and DFT • UVM testbench development from scratch, SystemC/C++ experience a plus • Python knowledge and scripting/automating DV flows • Good understanding of digital design, including RTL design, UVM, System Verilog and synthesis. • Knowledge of cryptography and data protection is a plus. • Excellent written and verbal communication skills, and the ability to work effectively in a team environment. Ability to work independently, under pressure and in a startup setting.
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