ASIC/FPGA Verification Designer

April 18

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Fidus Systems

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Electronic Product Development and Consulting • Signal Integrity • PCB Layout • FPGA timing closure • Signal Integrity consulting

51 - 200

Description

• Develop and execute comprehensive test plans, including both directed and random test cases, to verify the functionality of a block or subsystem. • Develop UVM environments and tests which comply with Client coding guidelines. • Debug and analyze issues at the system, FPGA, and ASIC levels. • Create and maintain test benches and simulation environments. • Write functional coverage items and close coverage buckets. • Collaborate with cross-functional teams to define verification methodologies and best practices. • Work closely with design engineers to ensure testability and coverage of designs. • Help to monitor regressions and triage as needed, assist in checklist closure. • Develop, implement, and execute functional and performance verification strategies. • Participate in design reviews and provide input on specifications and design trade-offs.

Requirements

• Bachelor's degree in Electrical/Computer Engineering or related field. • Minimum of 3 years of experience in ASIC/FPGA design verification • Proficient in Verilog/System Verilog/UVM • Strong knowledge of ASIC/FPGA design flows and methodologies. • Solid understanding of digital design fundamentals and verification techniques. • Experience with industry-standard protocols and interfaces (e.g., PCIe, DDR, Ethernet). • Practical experience with High Bandwidth Memory (HBM), robust security implementations, complex networking architectures, Advanced eXtensible Interface (AXI) integration, Network-on-Chip (NOC) design optimization, and ARM CPU subsystems. • Strong analytical and problem-solving skills. • Excellent communication and interpersonal skills. • Ability to work both independently and collaboratively in a fast-paced, deadline-driven environment.

Benefits

• 11 paid holidays • Generous Accrued Time Off increasing with years of service • Generous paid sick time