Senior ASIC Designer

March 19

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Fidus Systems

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Electronic Product Development and Consulting • Signal Integrity • PCB Layout • FPGA timing closure • Signal Integrity consulting

51 - 200

Description

• Collaborate with cross-functional teams to define and develop ASIC designs that meet project requirements • Write clear and concise block level technical specifications • Develop RTL code complying with Client coding guidelines • Work with engineers on the design of an IP, subsystem, SOC, or chiplet • Responsible for running lint, and CDC (Clock Domain Crossing), debugging issues, and creating appropriate waivers, • Propose and develop interface / block level assertions • Interact with physical design engineers on synthesis / timing / physical closure • Interact with verification engineers on block level verification closure • Review and close code coverage with verification engineers

Requirements

• Knowledge of semiconductor ASIC design methodologies and flows, knowledge of verification methodologies and flows is a plus • Minimum of 5 years of experience in ASIC design and development • Expertise in designing and implementing complex digital and mixed-signal ASIC circuits • Proficiency in RTL coding and verification using industry-standard tools (e.g., Verilog, SystemVerilog, UVM) • Strong programming skills including object-oriented programming • Working experience with digital logic design and verification • Practical experience in Ethernet, DDR/LPDDR, HBM, Security, Networking, AXI, NOC, ARM CPU subsystems • Demonstrate good analysis, problem-solving, and critical thinking skills, • Effective interpersonal, teamwork, and communication skills, • BS/MS degree in EE/CE or related technical field(s) is required.

Benefits

• Dynamic and supportive work environment • Opportunity to work on cutting-edge projects in a variety of industries • Real impact in the world of electronic product development