Director of Hardware Engineering

2 days ago

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Niobium Microsystems

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Microelectronics for Critical Systems.

Application Specific Integrated Circuit (ASIC) • Hardware • Cyber Security • Privacy • Fully Homomorphic Encryption (FHE)

11 - 50

💰 $90k Grant on 2021-11

Description

• Reporting to the VP of Engineering, the successful candidate will scale a team of Hardware Engineers to deploy Niobium’s Fully Homomorphic Encryption (FHE) accelerator. • This leadership role will involve owning the hiring, onboarding, managing, retaining, and scaling of our Hardware team while negotiating project priorities, resource managing, and collaborating with Engineering leaders. • This role will be influential in supporting our commercial business development. • The Niobium environment is fast-paced with overlapping priorities and requires the candidate to be highly flexible, agile, and resilient. • This position is integral to the success and growth of Niobium Microsystems.

Requirements

• Minimum of 10 years of experience in program optimization and engineering leadership • Industry track record of SoC design/architecture leadership, with the ability to manage and inspire a team of engineers • Record of building and leading successful teams through the delivery of commercial products • Experience in product lifecycle management, from ideation through to go-to-market strategies and launch • Ability to align technical capabilities with market demands • MS in Computer Science or Electrical Engineering, or equivalent hands-on industry experience applying hardware design technologies and methodologies • 10 or more years of relevant industry experience in the development of processors, co-processors, or hardware accelerator ASICs is strongly preferred • Expertise in RTL Design using HVLs and HDLs (SystemVerilog, Verilog), SoC Integration, and Interconnect Protocols (nice to have) • Experience in modeling SoC architectures with FPGAs and understanding bussing protocols such as AXI/AMBA/TileLink (nice to have) • Proficiency in interface components (PCIe, DDR, USB), SoC Place and Route, and SoC design with CHISEL (nice to have) • Familiarity with RISC-V architecture, Asynchronous Logic design techniques, and SoC verification (nice to have) • Strong background in DFT methodologies, Hardware Emulation, Hardware/Software co-simulation, and programming skills in C/C++/Python (nice to have) • Solid experience in SoC physical implementation, including timing constraint development, clock tree synthesis, timing closure, and signoff flows (nice to have) • Expertise in power domain design and analysis, physical verification (DRC, LVS, ERC, DFM), and the ability to create and extend automation flows (RTL to GDSII) (nice to have) • Experience with Synopsys tools flow (DC, ICC2, ICV, PT) is highly desirable (nice to have)

Benefits

• Competitive salaries scaled based on experience • Employer paid health care • Employer contribution to health savings account • Flexible time off • Flexible work location with remote options • 401K employer match