AI meets FM
AI meets FM is a venture capital firm that focuses on utilizing artificial intelligence to enhance the facilities management sector. The company specializes in connecting scale-ups with experienced partners, executives, and domain experts to accelerate growth and innovation in their ventures. By leveraging AI and industry expertise, AI meets FM aims to streamline operational processes and enhance product strategies for ambitious companies in the facilities management space.
Accredited Investors • Wealth Managers • RIAs • Investment Mangers • Investment Advisors
RTL Engineer - PCIe PHY Integration
November 4, 2024
AI meets FM
AI meets FM is a venture capital firm that focuses on utilizing artificial intelligence to enhance the facilities management sector. The company specializes in connecting scale-ups with experienced partners, executives, and domain experts to accelerate growth and innovation in their ventures. By leveraging AI and industry expertise, AI meets FM aims to streamline operational processes and enhance product strategies for ambitious companies in the facilities management space.
Accredited Investors • Wealth Managers • RIAs • Investment Mangers • Investment Advisors
📋 Description
• This is a remote position. • We are seeking a highly skilled RTL Engineer to join our team for a 6-month remote project focused on integrating a third-party PCIe PHY chip into a complex SoC design. • Your expertise in PCIe PHY integration, coupled with strong RTL design and verification skills, will be crucial to the success of this project. • Responsibilities: • PHY Integration: Integrate the third-party PCIe PHY IP into the SoC design. • Develop and verify the necessary RTL interfaces and control logic. • Ensure seamless communication and data transfer between the PHY and the SoC. • RTL Design: Design and implement RTL modules for PHY interface logic, configuration registers, and error handling mechanisms. • Adhere to design guidelines, coding standards, and synthesis constraints. • Timing Closure: Work closely with the physical design team to meet timing closure requirements. • Analyze timing reports and make necessary design adjustments.
🎯 Requirements
• Strong proficiency in Verilog or VHDL • 5+ years of experience in PCIe PHY integration, preferably Gen 5 or Gen 6 • Hands-on experience with Synopsys design tools (Synthesis, Formal Verification, STA) • Proficiency in scripting languages (Perl, Python, TCL) • Strong understanding of digital design principles, timing analysis, and power optimization • Excellent problem-solving and debugging skills • Good communication and teamwork abilities
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