5 days ago
• expertise to ensure our verification environment is highly reusable, scalable, modular and customizable across multiple interface IP’s in leading edge process nodes • create verification test plans and execute them including assertion-based, directed and randomized tests • create coverage metrics & reports and drive coverage goals and execution • develop firmware tests exercise critical IP training and other functionality • support customer adoption of these tests and other SOC tests with great efficiency • experience with Verification IP integration and/or development • experience with a coverage-driven verification methodology from planning through closure • support gate level verification and various back-annotation methodologies • support silicon bring-up and characterization including ATE vector creation • formal verification • create metrics to track verification progress
• 8+ years’ experience in verification leading the verification of complex highspeed interface IP like DDR/Serdes/high-speed IO • experience working on advanced technology nodes • strong exposure to UVM/OVM/eRM/VMM flow/methodologies • using VIP’s in verification flows • BIST methodologies and verification • low-power design and verification techniques (UPF/CPF) • low-power cell verification including isolation cells, retention cells etc. • protocol drivers, scoreboards, monitors, RAL models and assertions
• medical • dental • vision • 401K plan with company match • generous holiday & vacation leave
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