ASIC Design Engineer

October 20

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Cornelis Networks

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💰 $29M Series B on 2022-11

Description

• End-to-end SoC/ASIC development: Front-end standard cell ASIC development including RTL development, Design Verification, synthesis, and post-silicon validation. • Cross-functional collaboration and partnering with internal and external cross-functional teams, across all levels of the corporation. • Define, implement, debug, and deliver system solutions around purpose-built ASICs.

Requirements

• 5 + years' post-college experience with silicon development • 5 + years' post-college experience in digital design with one or more HDL language (System Verilog, Verilog, VHDL) • 5 + years' post-college experience in one or more scripting language (TCL, Python, Perl) • Understanding of Standard Cell ASIC development flow including digital design, IP integration, simulation and synthesis.