ASIC Design Verification Engineer
October 20
Description
• Participate in ground up development of UVM environments to verify RTL at block, unit, and SoC levels • Develop and execute functional tests according to verification test plans • Instrument TB for functional and code coverage and drive to closure based on the coverage metrics • Collaborate with cross-functional teams like design, software, emulation and silicon validation teams towards ensuring highest design quality
Requirements
• B. S. Degree in Computer Engineering, Computer Science, or Electrical Engineering • 5 + years of post-college experience writing code using System Verilog Language • Verification for complex SoCs with multiple clock and reset domains, using VCS or equivalent simulation tools • Debugging fails to the line of RTL, closing bug fixes, using Verdi or equivalent debug tools • Experience in ground up testbench development • Experience with revision control systems like Git or SVN
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