Senior ASIC Design Verification Engineer
October 20
Description
• Responsible for the verification closure of a design module or sub-system from test-planning, UVM based testbench development to verification closure. • Collaborate with cross-functional teams like design, software, emulation and silicon validation teams towards ensuring the highest design quality.
Requirements
• 10 + years of post-college experience with the following: • Writing code using System Verilog Language • Verification for complex SoCs that include multiple clock and reset domains, using VCS or equivalent simulation tools • Debugging fails to the line of RTL, closing out bug fixes, using Verdi or equivalent debug tools • Experience in ground up testbench development • Experience with revision control systems like Git or SVN etc
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