RTL Design Engineer

4 days ago

🏄 California – Remote

Although this job is listed in California, this company may be open to hiring remote in other states.

⏰ Full Time

🟡 Mid-level

🟠 Senior

🧑‍🔧 Mechanical Engineer

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Efabless Corporation

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Efabless Corporation is a pioneering platform that empowers innovation by democratizing chip design. It simplifies the chip creation process, making it accessible and affordable for startups, OEMs, and educational institutions. With a focus on open-source technology and support for hands-on learning, Efabless enables individuals to prototype and produce custom chips efficiently, fostering a community of chip designers and offering cost-effective solutions for intelligent product development.

Analog Mixed Signal IC & IP Modules • Crowdsourcing • Power Management IC • More than Moore • Sensor Interfaces

11 - 50 employees

Founded 2014

🔧 Hardware

📚 Education

🤝 B2B

📋 Description

• Develop, optimize, and maintain high-quality RTL code for digital blocks, ensuring it meets area, power, and timing constraints. • Define and develop SDC constraints to facilitate synthesis and timing closure, working closely with physical design and synthesis teams. • Collaborate with DFT and PnR teams to ensure designs meet testability and physical implementation requirements. • Support synthesis efforts, performing timing analysis and working through timing issues with cross-functional teams. • Leverage open-source (OS) tools and methodologies, where applicable, to enhance verification and design workflows. • Work closely with the verification team to debug and resolve functional issues, ensuring thorough testing and validation. • Participate in SoC-level integration, verification, and bring-up, with a focus on ensuring top-level functionality and performance. • Document design processes, contribute to design reviews, and uphold best practices in RTL development and verification.

🎯 Requirements

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field. • Minimum of 5 years of experience in RTL design, digital logic design, and verification. • Proficiency in Verilog/SystemVerilog for RTL coding and a deep understanding of digital design principles. • Strong experience with SDC (Synopsys Design Constraints) development for timing closure. • Hands-on experience with synthesis tools (e.g., Synopsys Design Compiler) and timing analysis. • Familiarity with DFT methodologies, including scan insertion and BIST. • Experience in place-and-route (PnR) processes, collaborating closely with physical design teams. • Knowledge of verification methodologies and experience working with verification teams to validate designs. • Familiarity with open-source tools and technologies in the digital design and verification space. • Strong problem-solving skills and the ability to work effectively in a collaborative team environment.