Senior ASIC Floorplan Design Engineer

November 5

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NVIDIA

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GPU-accelerated computing • artificial intelligence • deep learning • virtual reality • gaming

10,000+

Description

• Develop and optimize floorplans during early chip development. • Drive area review process and collaborate with design teams. • Solve timing and routing congestion issues by influencing design decisions. • Build tools and improve infrastructure to optimize chip area and speed.

Requirements

• Masters Degree in Electrical Engineering, Computer Science, or Computer Engineering or equivalent experience • 6+ years of relevant work experience • A deep hardware engineering background with a concentration in VLSI and/or Computer Architecture. • Experience in Verilog, System Verilog or similar HVL • Experience with CAD and physical design methodologies (flow and tool development), chip floorplan, power/clock distribution, packaging, P&R and timing closure. • Strong communication and interpersonal skills and ability & desire to work as a great teammate should be displayed in your interview. • Python, Perl and C/C++ programming language experience

Benefits

• Eligible for equity and benefits.