December 14
• Develop your skills with Placement, Timing Closure & New Part/Board Setup in Intel Quartus and Agilex based devices • Work with Hardware design to define and capture the FPGA configuration requirements • Be involved in the Design of RTL code for product inclusion • Develop and maintain Continuous Integration processes for FPGA/ASIC build flows & applications by accessing and using tools like Jenkins, GitHub etc. • Troubleshoot and triage on the build pipeline, infrastructure and tools issues • Execute medium to large tasks independently & provide regular updates to stakeholders • Develop mock-ups or requirement prototypes for features of moderate to high complexity and effectively articulate the requirements to relevant stakeholders
• A minimum of 6 years experience as an ASIC/FPGA Designer • A degree in Electrical Engineering or a related field • Solid experience in Altera/Quartus FPGA build and release process • Expertise in operating Linux environment with good command over any scripting language such as Shell, Python, etc. • Deep experience with Altera/Intel and Cadence EDA tools • Experience with simulation, synthesis, timing closure and backend FPGA/ASIC tool flow • Strong hands-on knowledge of Python, Bash, Jenkins, GitHub CI/CD pipeline tools • Strong troubleshooting and triaging capabilities, passionate to learn & quickly adapt to the new technology, process knowledge. • Bonus: knowledge of Intel FPGA design flow and tools, AMD/Xilinx FPGA design flow and tools, protocols related to highspeed, low latency, switching data path ASIC/FPGA verification methodologies such as UVM System Verilog, low power design techniques for ASIC/FPGA Design optimization for speed/timing, power, area
• Competitive salary and bonus program • Health benefits package • Employee assistance program • Generous time off programs
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