Design Verification Engineer

21 hours ago

🇺🇸 United States – Remote

🏈 Ohio – Remote

Although this job is listed in Ohio, this company may be open to hiring remote in other states.

⏰ Full Time

🟡 Mid-level

🟠 Senior

✍️ Designer

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Description

• Develop and execute verification plans for digital designs using SystemVerilog and UVM • Create and maintain testbenches, test cases, and test vectors • Contribute to the development of novel methodologies and verification techniques • Run simulations to verify design against specifications • Analyze results, identify issues, and debug designs • Implement coverage tracking and metrics • Document plans, environments, test cases, and all results for a comprehensive record of all verification strategies

Requirements

• Bachelor’s degree in Electrical Engineering, Computer Engineering, or related field • Minimum of 3 years of hands-on experience in SoC verification using UVM • Experience using Synopsys verification tools such as VCS, Verdi, and Spyglass • Experience writing and debugging RTL using SystemVerilog • Programming experience using C, C++, and/or Python • Familiarity with digital design concepts and ASIC development flow • Strong analytical and problem-solving skills • Ability to multi-task and prioritize in a fast-paced environment; managing multiple complex, multidisciplinary tasks and projects • Ability to work collaboratively across teams and communicate effectively • Attention to detail and remarkable eye for accuracy • Willingness to learn and develop new skills

Benefits

• Competitive salaries scaled based on experience • Employer paid health care • Employer contribution to health savings account • Flexible time off • Flexible work location with remote options • 401K employer match